DocumentCode :
3378174
Title :
Optimization of lightly-doped-drain (LDD) structure for sub-quarter-μm devices using statistical design and response surface methodology
Author :
Tsai, Jiunn-Yann ; Zhang, Kevin X. ; Osburn, Carlton M.
Author_Institution :
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
fYear :
1995
fDate :
31 May-2 Jun 1995
Firstpage :
285
Lastpage :
290
Abstract :
A Lightly-Doped-Drain (LDD) structure was optimized by extensive process and device simulations with advanced mobility and impact ionization models for sub-quarter-μm devices. A quadratic response-surface-model (RSM) was derived from Design-of-Experiment (DOE) with input variables related to the drain structure. The saturation current (Isat), the off-state current (Ioff), and the maximum substrate current (Isub) were treated as figure-of-merits (FOM´s) for tradeoffs between device performance, device short channel effect and device reliability. The source/drain junction depth had little effect on the three FOM´s. This enhanced the concept of drain-decoupling by separating the drain contact to channel and the drain contact to metal silicide. Even though the LDD tab does not necessarily improve the device reliability, it does provide a practical way of forming ultra-shallow junctions to meet the scaling requirement. The tab length has to be reduced to improve the driving capability, while the tab dose has to be increased to minimize the sensitivity of the driving capability to spacer length variations. Devices with optimized LDD drain structure were fabricated to verify the RSM prediction, and excellent device characteristics in agreement with simulation have been achieved
Keywords :
MOSFET; carrier mobility; design of experiments; impact ionisation; optimisation; semiconductor device models; semiconductor device reliability; design-of-experiment; device simulation; drain-decoupling; figure-of-merits; impact ionization; lightly-doped-drain structures; metal silicide; mobility; off-state current; optimization; process simulation; quadratic response-surface-model; reliability; saturation current; scaling; short channel effect; spacer length; statistical design; sub-quarter-micron devices; substrate current; tab length; ultra-shallow junction; Computational modeling; Design optimization; Hot carriers; Impact ionization; Input variables; MOSFET circuits; Predictive models; Response surface methodology; Silicides; US Department of Energy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, Systems, and Applications, 1995. Proceedings of Technical Papers. 1995 International Symposium on
Conference_Location :
Taipei
ISSN :
1524-766X
Print_ISBN :
0-7803-2773-X
Type :
conf
DOI :
10.1109/VTSA.1995.524705
Filename :
524705
Link To Document :
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