Redundant states in test control block design

The number of states in sequential circuit designs does not usually equal to 2ⁿ This results in a number of redundant state codes. It has been accepted that redundant state codes are used as don´t cares in the next-state equations. The target is a reduction of the hardware costs. In doing so the behaviour of the circuit in redundant states has not been specified in advance. Error handling and testability may be a serious problem. This paper shows there is an alternative. Redundant states can be fully specified in a simple and meaningful way, often with even better hardware efficiency than a state assignment with don´t cares. Some additional results in encoding test control blocks are also given