Unified analytical global placement for large-scale mixed-size circuit designs

A modern chip often contains large numbers of pre-designed macros (e.g., embedded memories, IP blocks) and standard cells, with very different sizes. The fast-growing design complexity with large-scale mixed-size macros and standard cells has caused significant challenges to modern circuit placement. Analytical algorithms have been shown to be most effective for standard-cell placement, but the problems with the rotation and legalization of large macros impose intrinsic limitations for analytical placement. Consequently, most recent works on mixed-size placement resort to combinatorial macro placement. Instead, this paper presents the first attempt to resolve the intrinsic problems with a unified analytical approach. Unlike traditional analytical placement that uses only wire and density forces to optimize the positions of circuit components, we present a new force, the rotation force, to handle macro orientation for analytical mixed-size placement. The rotation force tries to rotate each macro to its desired orientation based on the wire connections on this macro. A cross potential model is also proposed to increase the rotation freedom during placement. The final orientation of each macro with legalization consideration is then determined by mathematical programming at the end of global placement. Experimental results show the effectiveness and efficiency of our approach. Compared with state-of-the-art mixed-size placement approaches (such as FLOP, CG, and MP-tree), our approach achieves the best average wirelength efficiently.