Title :
Clocking PLL solutions for high speed computer
Author_Institution :
Digital Equipment Corp., Marlboro, MA, USA
fDate :
31 May-2 Jun 1995
Abstract :
The phase-locked loop (PLL) with excellent power supply rejection ratio (PSRR), as an alternative to surface acoustical wave (SAW) oscillator, provides comparable jitter performance in high speed clocking applications where minimum power supply noise can not be guaranteed. PLL´s offer not only excellent price/performance but also flexible functionality including smooth frequency transition for power down and electromagnetic compatibility (EMC) applications
Keywords :
computers; digital computers; electromagnetic compatibility; jitter; phase locked loops; synchronisation; timing circuits; EMC applications; clocking PLL; electromagnetic compatibility; high speed clocking applications; high speed computer; jitter performance; phase-locked loop; power supply rejection ratio; Application software; Clocks; Electromagnetic compatibility; Jitter; Oscillators; Phase locked loops; Phase noise; Power supplies; Signal to noise ratio; Surface acoustic waves;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1995. Proceedings of Technical Papers. 1995 International Symposium on
Conference_Location :
Taipei
Print_ISBN :
0-7803-2773-X
DOI :
10.1109/VTSA.1995.524718
