Synchronization of on-chip serial interconnect transceivers using Delay Locked Loop (DLL)

In literature delay locked loop (DLL) architecture is used for synchronizing the on-chip serial interconnect transceivers instead of phase locked loops (PLL) due to increased stability and low jitter. In this paper, the design and implementation of a Mixed-Delay Locked Loop (DLL) for on chip serial transceiver is carried out with a modified architecture, which takes less number of clock cycle for locking and has low jitter. The voltage controlled delay line (VCDL) of the proposed DLL is designed with current-starved inverters, which are normally used in PLLs. The charge pump with symmetric load is used to obtain wide frequency range of operation. The proposed DLL circuit is implemented in UMC 0.18μm technology and the post-layout simulations are carried out in CADENCE Spectre tool. From the simulations, it is observed that the proposed mixed DLL circuit operates to the frequency ranges from 650 MHz to 1.2 GHz with a locking period of 4 to 8 clock cycles and has a jitter of approximately 10 psec.