Title :
High-speed zero-sum detection
Author :
Weinberger, Arnold
Author_Institution :
P.O. Box 390 International Business Machines Corporation Poughkeepsie, New York 12602
Abstract :
A common requirement accompanying high-speed parallel addition is the early detection that the sum is equal to zero. Normally, this condition is detected from the sum, generally at least two logic gate levels after the sum.
Keywords :
Adders; Bismuth; Business; Delay; Equations; Logic gates;
Conference_Titel :
Computer Arithmetic (ARITH), 1975 IEEE 3rd Symposium on
Conference_Location :
Dallas, TX, USA
DOI :
10.1109/ARITH.1975.6157008
