Xilinx FPGA design in a group environment using VHDL and synthesis tools

The use of VHDL and synthesis tools has been shown to be well suited to achieving the objectives in a group design environment. The expressiveness of VHDL lends itself to group discussion and with synthesis, the outcome is correct by construction and can be verified rapidly in a true system environment built around a Xilinx FPGA. Not surprisingly however since this year has seen the first full run of students through the course there have been problems. Students in their second year are not sufficiently mature to accept that fighting the CAD system and winning is a necessary part of becoming a successful designer and so they complain continually about the apparent dumbness of Autologic, its slowness and its seemingly obscure error messages. The complaints about the VHDL compiler run in a similar vein. Perhaps one day CAD tools of this complexity really will become quicker and less hostile. However, what this year´s group cannot appreciate is how much more productive and successful they have been than have several years of preceding cohorts using traditional design methods with schematic capture. More help will of course be available on how to write VHDL to achieve more efficient synthesis as more experience is gained by staff of the seemingly infinite set of traps waiting to catch the novice designer