A new DFT technique to reduce test duration for sequential circuits

Sequential ATPGs exist that are able to handle appreciable degree of sequentiality, thus allowing to use partial scan implementations with suitable fault coverage. Nevertheless, with these scan methods the test duration remains often prohibitive due to long scan-in and -out operations. The method described is based on the emulation of several easily testable configurations, during the test operation. The various configurations are generated in such a way that they exhibits a clearly reduced sequentiality, this sequentiality being expressed in terms of number and length of cycles and sequential depth. Results have been obtained on the set of sequential ISCAS89 benchmarks [Brg89] in the case of a two-configuration implementation. For each circuit, the derived configurations are found to have their sequentiality strongly reduced (in terms of number and length of cycles and sequential depth) in comparison with that of the initial circuit [Ber93]