Abstract :
The following topics are dealt with: VLSI design and circuits; CMOS image sensor; macro-pipelined architecture; timing optimisation; high reliable digital signal processor; differential fault analysis; photoelectric encoder system; multi-standard decoder; logic gate; high speed face detection architecture; power management IC; current mode DC-DC converter; CMOS low-dropout; analogue technique; class-AB CMOS buffer; fully differential amplifier; double charge pump circuit; CMOS charge pump; signal conditioner IC; EEG-ECG signal recording applications; chip multiprocessor; VHDL and system Verilog; high speed CMOS image; homogeneous multiprocessor system-on-chip; quartz crystal microbalance biosensors; NoC-based multicore architecture; wireless communications; robust frame synchronisation; high-efficiect baseband transceiver; test, reliability, and fault tolerance; NAND flash memories; SRAM weak cell testing; immune latch circuit design; electrostatic discharge protection; silicon nanowire technology; software-hardware co-debug platform; GGnMOS ESD protection device; memristor logic, and resistive memory; phase change memory; multidielectric Green function; three-dimensional network-on-chip; low-leakage flip-flop FPGA emulation; dual-output basic logic element; high speed ASIC design; mixed polarity Reed-Muller expression; annealing genetic algorithm; MEMS technology, device, and circuit; buck DC-DC converter; power HEMT; MEMS gyroscope drive; inductorless CMOS LNA; second-order temperature compensation; current source inverter structure; low-kickback preamplifier; large-signal MOSFET modelling; pipelined ADC; wireless transceiver and building blocks; wireless sensor network; reconfigurable low pass filter; and embedded system.
Keywords :
CMOS image sensors; DC-DC power convertors; MOSFET; VLSI; analogue-digital conversion; biosensors; circuit optimisation; electrocardiography; electroencephalography; embedded systems; flip-flops; hardware description languages; logic gates; low-pass filters; micromechanical devices; reliability; transceivers; CMOS charge pump; CMOS image sensor; CMOS low-dropout; EEG-ECG signal recording application; GGnMOS ESD protection device; MEMS gyroscope drive; MEMS technology; NAND flash memory; NoC-based multicore architecture; SRAM weak cell testing; VHDL; VLSI design; analogue technique; annealing genetic algorithm; buck DC-DC converter; chip multiprocessor; class-AB CMOS buffer; current mode DC-DC converter; current source inverter structure; differential fault analysis; double charge pump circuit; dual-output basic logic element; electrostatic discharge protection; embedded system; fault tolerance; fully differential amplifier; high speed ASIC design; high speed face detection architecture; high-efficiect baseband transceiver; homogeneous multiprocessor system-on-chip; immune latch circuit design; inductorless CMOS LNA; large-signal MOSFET modelling; logic gate; low-kickback preamplifier; low-leakage flip-flop FPGA emulation; macropipelined architecture; memristor logic; mixed polarity Reed-Muller expression; multi-standard decoder; multidielectric Green function; phase change memory; photoelectric encoder system; pipelined ADC; power HEMT; power management IC; quartz crystal microbalance biosensor; reconfigurable low pass filter; reliability; reliable digital signal processor; resistive memory; robust frame synchronisation; second-order temperature compensation; signal conditioner IC; silicon nanowire technology; software-hardware co-debug platform; speed CMOS image; system Verilog; three-dimensional network-on-chip; timing optimisation; wireless communication; wireless sensor network; wireless transceiver;
Conference_Titel :
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location :
Xiamen
Print_ISBN :
978-1-61284-192-2
Electronic_ISBN :
2162-7541
DOI :
10.1109/ASICON.2011.6157042