Analysis of voltage forcing consequences during in-circuit testing

In-circuit testing enables one to verify the functionality of electrical connections on the board and of components mounted on it. Despite its different drawbacks, mainly related to the potential damage that can be caused to the active components mounted on the board, this technique is still the most commonly used one as it presents almost no limitation concerning the kind of devices to be tested and the kind of failure to be detected. For this reason PCB producers are very interested in understanding the limits of this technique. The authors present a study of problems that could arise when applying the in-circuit technique to new components. Failure mechanisms which can occur during the tests are outlined and some results obtained with R/W RAM in 0.8 μm CMOS technology are discussed