• DocumentCode
    3379262
  • Title

    A Single-Bit Digital DC-Blocker Using Ternary Filtering

  • Author

    Sadik, Amin Z. ; Hussain, Zahir M. ; O´Shea, Peter

  • Author_Institution
    Sch. of Eng. Syst., Queensland Univ. of Technol., Melbourne, VIC
  • fYear
    2005
  • fDate
    21-24 Nov. 2005
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    In this paper, a single-bit DC-blocker is presented. It is comprised of a ternary filtering stage preceded by a sigma-delta modulator. Different techniques are used to generate the ternary taps for hardware and performance optimization. Both the input and the output of this DC-blocker are assumed in single-bit format. The proposed DC-blocker can easily be implemented with FPGA.
  • Keywords
    FIR filters; field programmable gate arrays; sigma-delta modulation; FPGA; performance optimization; sigma-delta modulator; single-bit digital DC-blocker; ternary filtering; Australia; Digital filters; Digital modulation; Digital signal processing; Filtering; Finite impulse response filter; Frequency; Hardware; Limit-cycles; Systems engineering and theory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    TENCON 2005 2005 IEEE Region 10
  • Conference_Location
    Melbourne, Qld.
  • Print_ISBN
    0-7803-9311-2
  • Electronic_ISBN
    0-7803-9312-0
  • Type

    conf

  • DOI
    10.1109/TENCON.2005.301222
  • Filename
    4085052
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3379262