DocumentCode
3379301
Title
An optimized architecture to perform image compression and encryption simultaneously using modified DCT algorithm
Author
Sateesh, S.V.V. ; Sakthivel, Rathinasamy ; Nirosha, K. ; Kittur, Harish M.
Author_Institution
VIT Univ., Vellore, India
fYear
2011
fDate
21-22 July 2011
Firstpage
442
Lastpage
447
Abstract
Traditional fast Discrete Cosine Transforms (DCT)/ Inverse DCT (IDCT) algorithms have focused on reducing the arithmetic complexity. In this manuscript, we implemented a new architecture simultaneous for image compression and encryption technique suitable for real-time applications. Here, contrary to traditional compression algorithms, only special points of DCT outputs are calculated. For the encryption process, LFSR is used to generate random number and added to some DCT outputs. Both DCT algorithm and arithmetic operators used in algorithm are optimized in order to realize a compression with reduced operator requirements and to have a faster throughput. High Performance Multiplier (HPM) is being used for integer multiplications. Simulation results show the compression ratio around 66% and a PSNR about 24dB. The throughput of this architecture is 624 M samples/s with a clock frequency of 78 MHz.
Keywords
computational complexity; cryptography; data compression; discrete cosine transforms; image coding; LFSR; arithmetic complexity; discrete cosine transforms; high performance multiplier; image compression; image encryption; inverse DCT; modified DCT algorithm; optimized architecture; Clocks; Computer architecture; Discrete cosine transforms; Encryption; Image coding; Multiplexing; ASIC; Carry select adder; DCT; FPGA; HPM; JPEG; LFSR;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing, Communication, Computing and Networking Technologies (ICSCCN), 2011 International Conference on
Conference_Location
Thuckafay
Print_ISBN
978-1-61284-654-5
Type
conf
DOI
10.1109/ICSCCN.2011.6024591
Filename
6024591
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