A novel method for storage architecture of pipeline FFT processor

This paper presents a new method to improve the storage architecture of the pipeline fast Fourier transform (FFT) processor. The main idea is interpreted as follows. The FFT butterfly calculation can operate with the same reading and writing address every time. In this case, each butterfly operation unit (BFU) can read and write on the same RAM at one time. Then the pipeline purpose is achieved by cyclically alternating the associated orders of BFUs and RAMs. Compared to the traditional project, this method can save almost 50% storage devices without sacrificing performance. It has been proven correct and feasible with the hardware design and verification.