Reduction of testing power with pulsed scan flip-flop for scan based testing

Author

Valibaba, D. Satya ; Sivanantham, S. ; Mallick, P.S. ; Perinbam, J.R.P.

Author_Institution

Sch. of Electron. Eng., VIT Univ., Vellore, India

fYear

2011

fDate

21-22 July 2011

Firstpage

526

Lastpage

531

Abstract

In this paper, a new scan flip-flop is proposed for low power testing. Different flip-flops (Master-slave, hybrid, pulse triggered) are reviewed and evaluated their performance using ELDO simulator with TSMC 180 nm CMOS technology. Based on this evaluation, pulsed triggered flip-flop is selected as scan flip-flop because of lower transition power. Comparison of proposed scan flip-flop with existing mux based master-slave scan flip-flop is performed at the layout level. Experimental results on ISCAS89 benchmark circuit show that the proposed scan flip-flop can be used to reduce the test power.

Keywords

CMOS integrated circuits; flip-flops; integrated circuit testing; ELDO simulator; TSMC 180 nm CMOS technology; low power testing; master-slave scan flip-flop; pulsed scan flip-flop; pulsed triggered flip-flop; scan based testing; testing power; Automatic test pattern generation; CMOS technology; Flip-flops; Latches; Switches; Very large scale integration; DFT; low power testing; pulsed flip-flop; scan flip-flop; scan-based testing; tests power reduction;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing, Communication, Computing and Networking Technologies (ICSCCN), 2011 International Conference on

Conference_Location

Thuckafay

Print_ISBN

978-1-61284-654-5

Type

conf

DOI

10.1109/ICSCCN.2011.6024608

Filename

6024608