DocumentCode
3379712
Title
Multi-stage power gating based on controlling values of logic gates
Author
Jin, Yu ; Kimura, Shinji
Author_Institution
Grad. Sch. of IPS, Waseda Univ., Kitakyushu, Japan
fYear
2011
fDate
25-28 Oct. 2011
Firstpage
79
Lastpage
82
Abstract
As the CMOS technology scales down, low power technologies have been expected to reduce leakage power of the CMOS device. Controlling value based power gating is a fine-grained active mode power gating approach using the controlling values of logic elements. In this method, one input of a logic gate taking the controlling value stops the power supply to the logic blocks generating other inputs. In this paper, we propose a multi-stage power gating method based on controlling values by stopping the power supply of several gates in the power controlled blocks. Experimental results show that the proposed approach increases the number of power-off elements by 26.7% in average compared with the single-stage power-gating method.
Keywords
CMOS logic circuits; logic gates; low-power electronics; CMOS device; CMOS technology; controlling value; leakage power reduction; logic blocks; logic elements; logic gates; low-power technologies; multistage power gating method; power supply; power-controlled blocks; Delay; Logic gates; Silicon; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location
Xiamen
ISSN
2162-7541
Print_ISBN
978-1-61284-192-2
Electronic_ISBN
2162-7541
Type
conf
DOI
10.1109/ASICON.2011.6157127
Filename
6157127
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