Implementation of low power RAM in GDI technique with full swing

Low power design has become one of the primary focuses in digital VLSI circuits. Technology scaling demands a decrease in both supply voltage (V_DD) and threshold voltage (V_TH). This leads to increase in sub-threshold leakage power. In VLSI chips, the power consumption is more in Flip-Flops. So the primary objective of using sub-threshold circuits is to reduce the energy. This paper presents about a low power RAM implemented in the proposed Gate-Diffusion-Input (GDI) technique that provides full swing. The design is simulated in 0.18μm TSMC technology with the supply voltage of 1.8V using Mentor Graphics Design Architect.