DocumentCode
3379967
Title
Circuit optimization techniques in DROID
Author
Chen, Hau-Yung ; Agarwala, Sanjive ; Dutta, Santanu ; Matzke, Doug ; Bosshart, Patrick ; Lusky, Steve ; Kollaritsch, Paul
Author_Institution
Texas Instruments Inc., Dallas, TX, USA
fYear
1991
fDate
22-24 May 1991
Firstpage
162
Lastpage
166
Abstract
Circuit-level optimization techniques such as buffer insertion, gate input reordering and transistor sizing are commonly practiced by circuit designers to deliver high performance circuits. All these techniques are indispensable in shortening the design cycle and in improving the delay performance. The authors describe the algorithms implementing these circuit optimization techniques which allow push-button, high-performance synthesis within the DROID Auto-Full-Custom design system
Keywords
application specific integrated circuits; circuit layout CAD; logic CAD; optimisation; Auto-Full-Custom design system; DROID; algorithms; buffer insertion; gate input reordering; high-performance synthesis; push-button; transistor sizing; Algorithm design and analysis; Capacitance; Circuit optimization; Circuit synthesis; Delay effects; Design optimization; Instruments; Logic circuits; Timing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on
Conference_Location
Taipei
ISSN
1524-766X
Print_ISBN
0-7803-0036-X
Type
conf
DOI
10.1109/VTSA.1991.246690
Filename
246690
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