Simultaneous topology selection and timing assignment for LSI circuits based on semi-analytical delay-area expression

The author describes a new area optimization method for LSI circuits based on a semi-analytical delay-area expression, which simultaneously gives the optimal topology and delay time for each logic block under a given permissible total delay time and load conditions. Also, a quick estimation technique for parameters appearing in the area-delay expression is given out, and a practical method is presented for realization of topology selection and timing assignment by combining the dynamic and nonlinear programming. From experimental examples with thousands of transistors, the circuit topology and transistor sizes can be optimized simultaneously in a practical CPU time