FFT implementation with Multi-operand floating point units

Author

Zhang, Zhang ; Wang, Dongge ; Pan, Yuteng ; Wang, Dan ; Zhou, Xiaofang ; Sobelman, Gerald E.

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2011

fDate

25-28 Oct. 2011

Firstpage

216

Lastpage

219

Abstract

In this paper we propose two new design techniques for floating point arithmetic units used in DSP applications, and apply them in the design of two multi-operand units for high-radix FFTs. These two multi-operand arithmetic units are a Modified two term Dot Product (MDP) unit and a Multi-operand Add-Sub unit (MAS). A radix-4 FFT butterfly computation block is implemented efficiently with these multi-operand units. Synthesis results show that the butterfly unit built with our design is about 43% faster and 9.5% smaller than a conventional implementation.

Keywords

fast Fourier transforms; floating point arithmetic; DSP applications; FFT implementation; floating point arithmetic units; high-radix FFT; modified two term dot product; multioperand add-sub unit; multioperand arithmetic units; multioperand floating point units; radix-4 FFT butterfly computation block; Adders; Reduced instruction set computing; Floating-point Arithmetic; Multi-operand Floating-point operations; Radix-4 FFT Butterfly;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC (ASICON), 2011 IEEE 9th International Conference on

Conference_Location

Xiamen

ISSN

2162-7541

Print_ISBN

978-1-61284-192-2

Electronic_ISBN

2162-7541

Type

conf

DOI

10.1109/ASICON.2011.6157160

Filename

6157160