Improvement of Wallace multipliers using parallel prefix adders

Arithmetic & Logic Unit (ALU) of a processor, when used for scientific computations, will spend more time in multiplications. Wallace multipliers perform in parallel, resulting in high speed. It uses full adders and half adders in their reduction phase. Reduced Complexity Wallace multiplier will have fewer adders than normal Wallace multiplier. In both multipliers, at the final stage, Carry propagating adder is used, which contributes to delay. This paper proposes, employing parallel prefix adders (fast adders) at the final stage of Wallace multipliers to reduce the delay.