Variation-Aware Comparative Study of 10-nm GAA Versus FinFET 6-T SRAM Performance and Yield

Author

Peng Zheng ; Yi-Bo Liao ; Damrongplasit, N. ; Meng-Hsueh Chiang ; Tsu-Jae King Liu

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Univ. of California at Berkeley, Berkeley, CA, USA

Volume

61

Issue

12

fYear

2014

fDate

Dec. 2014

Firstpage

3949

Lastpage

3954

Abstract

This paper benchmarks the performance of gate-all-around (GAA) MOSFETs against that of optimized silicon-on-insulator FinFETs at 10-nm gate length. Variability in transistor performance due to systematic and random variations is estimated with the aid of TCAD 3-D device simulations, for both device structures. The yield of six-transistor SRAM cells implemented with these advanced MOSFET structures is then investigated via a calibrated physically based compact model. The GAA MOSFET technology is projected to provide for 0.1 V lower minimum cell operating voltage with reduced cell area.

Keywords

MOSFET; SRAM chips; semiconductor device models; silicon-on-insulator; technology CAD (electronics); GAA MOSFET; TCAD 3D device simulations; advanced MOSFET structures; calibrated physically based compact model; gate-all-around MOSFET; optimized silicon-on-insulator FinFET; random variations; six-transistor SRAM cells yield; size 10 nm; systematic variations; transistor performance variability; FinFETs; Logic gates; MOSFET; Performance evaluation; SRAM cells; Solid modeling; FinFET; gate-all-around (GAA); six-transistor (6-T) SRAM; variation; variation.;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2014.2360351

Filename

6951350