A software/hardware co-debug platform for multi-core systems

Author

Lee, Kuen-Jong ; Su, Alan ; Chen, Long-Feng ; Jhou, Jia-Wei ; Kuo, Jiff ; Liu, Mark

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

fYear

2011

fDate

25-28 Oct. 2011

Firstpage

259

Lastpage

262

Abstract

In this paper we present a software/hardware co-debug platform to deal with the various debug problems in multiple-core SOC systems with multiple-clock domains. This platform allows designers to debug embedded processors, buses, IP cores, as well as the application programs being developed. It can be used at various design and manufacturing stages including component development, hardware/software co-design, system prototyping, and post-silicon debugging. Three major mechanisms are integrated into this platform, namely a software debug mechanism for multi-core programming, an on-chip hardware debug mechanism for various hardware IPs, and a two-way cross trigger mechanism to synchronize the debug processes of software and hardware. Experimental results on a FPGA prototyping board demonstrate the effectiveness and efficiency of this platform in identifying the root causes of failures for multiple-core SOC systems with multiple-clock domains.

Keywords

clocks; computer debugging; embedded systems; field programmable gate arrays; hardware-software codesign; logic circuits; microprocessor chips; multiprocessing systems; system-on-chip; FPGA prototyping; IP cores; application programs; buses; component development; embedded processors; hardware/software codesign; multiple-clock domains; multiple-core SOC systems; post-silicon debugging; software/hardware co-debug platform; system prototyping; Clocks; Hardware; Software;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC (ASICON), 2011 IEEE 9th International Conference on

Conference_Location

Xiamen

ISSN

2162-7541

Print_ISBN

978-1-61284-192-2

Electronic_ISBN

2162-7541

Type

conf

DOI

10.1109/ASICON.2011.6157171

Filename

6157171