Reliability studies of a 32nm System-on-Chip (SoC) platform technology with 2nd generation high-k/metal gate transistors

Author

Rahman, A. ; Agostinelli, M. ; Bai, P. ; Curello, G. ; Deshpande, H. ; Hafez, W. ; Jan, C.-H. ; Komeyli, K. ; Park, J. ; Phoa, K. ; Tsai, C. ; Yeh, J.-Y. ; Xu, J.

Author_Institution

Logic Technol. Dev. Quality & Reliability, Intel Corp., Hillsboro, OR, USA

fYear

2011

fDate

10-14 April 2011

Abstract

Extensive reliability characterization of a state of the art 32nm strained HK/MG SoC technology with triple transistor architecture is presented here. BTI, HCI and TDDB degradation modes on the Logic and I/O (1.2V, 1.8V and 3.3V tolerant) transistors are studied and excellent reliability is demonstrated. Importance of process optimizations to integrate robust I/O transistors without degrading performance and reliability of Logic transistors emphasized. Finally, Intrinsic and defect reliability monitoring for HVM are addressed.

Keywords

electric breakdown; integrated circuit reliability; logic gates; system-on-chip; transistors; 2^nd generation high- K-metal gate transistor; BTI degradation; HCI degradation; I-O transistor; SoC; TDDB degradation; logic transistor; process optimization; reliability study; size 32 nm; system-on-chip platform technology; voltage 1.2 V; voltage 1.8 V; voltage 3.3 V; Degradation; Dielectrics; Integrated circuit reliability; Logic gates; MOS devices; Transistors; BTI; CMOS; High-K dielectric; Reliability; SILC; SoC; TDDB; breakdown; metal gate;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2011 IEEE International

Conference_Location

Monterey, CA

ISSN

1541-7026

Print_ISBN

978-1-4244-9113-1

Electronic_ISBN

1541-7026

Type

conf

DOI

10.1109/IRPS.2011.5784531

Filename

5784531