A 55nm ultra high density two-port register file compiler with improved write replica technique

In this paper a two-port register file (RF) compiler with ultra high density design is presented. The memory implemented using a single port memory core, which is combined with a smart address selector circuit to reduce peripheral devices number and thus the silicon area is decreased significantly. The separate read and write replica scheme are implemented, with the improved write replica technique the memory compiler can accurately track the write timing over a wide range of memory array sizes and PVT variation. A test-chip with 13 embedded RF memories has been fabricated in UMC 55nm logic standard performance low-K process. The ultra high density design can markedly save 44.0% silicon area compared to conventional two-port RF (with 8T dual-port memory core) and only 4.3% area overhead compared to single-port RF (with 6T single-port memory core) for a 55nm 72Kb memory.