Split-gate flash memory for automotive embedded applications

Author

Chu, Y.S. ; Wang, Y.H. ; Wang, C.Y. ; Lee, Y.-H. ; Kang, A.C. ; Ranjan, R. ; Chu, W.T. ; Ong, T.C. ; Chin, H.W. ; Wu, K.

Author_Institution

Technol. Quality & Reliability Div., Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan

fYear

2011

fDate

10-14 April 2011

Abstract

An embedded split-gate flash memory based on 65nm logic process technology has been developed. The design rules for split-gate flash macro´s testability and reliability are discussed. An automotive grade flash memory with 100K endurance, 10 years, 125°C data retention, and 1-ppm requirement has been demonstrated with a comprehensive dielectric screen methodology. Both erase time push out and data retention dominant mechanisms are thoroughly studied with intrinsic lifetime and large sample certification. An automotive embedded split-gate flash solution in 65nm technology is ready for commercialization.

Keywords

automotive electronics; flash memories; logic circuits; automotive embedded applications; dielectric screen methodology; logic process technology; reliability; split-gate flash memory; testability; Automotive engineering; Dielectrics; Logic gates; Reliability; Split gate flash memory cells; Stress; data retention; endurance; erase time push out; split-gate memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2011 IEEE International

Conference_Location

Monterey, CA

ISSN

1541-7026

Print_ISBN

978-1-4244-9113-1

Electronic_ISBN

1541-7026

Type

conf

DOI

10.1109/IRPS.2011.5784547

Filename

5784547