DocumentCode :
3381299
Title :
A new event driven testbench synthesis engine for FPGA emulation
Author :
Huang, Haocheng ; Ruan, Aiwu ; Liao, Yongbo ; Zhu, Jianhua ; Wang, Lin ; Xiang, Chuanyin ; Li, Pin
Author_Institution :
State key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China
fYear :
2011
fDate :
25-28 Oct. 2011
Firstpage :
373
Lastpage :
376
Abstract :
FPGA emulation has long provided the highest performance. However, designers have to restrict their coding style or transforming a huge unsynthesizable testbench into synthesizable one by themselves due to usually unsynthesizable testbench. We address this problem by presenting a new event driven testbench synthesis engine called BeEmu (Behavior-Level Emulator) to translate the behavioral testbench into synthesizable one for FPGA emulation. The proposed testbench synthesis engine is built by hardware constructs in terms of event driven model to correspond with testbench. Experiments demonstrate that our proposed engine can not only have a high simulation speed, but cover more HDL syntax as well.
Keywords :
electronic engineering computing; field programmable gate arrays; logic design; BeEmu; FPGA emulation; HDL syntax; behavior-level emulator; coding style; event driven testbench synthesis engine; Engines; Field programmable gate arrays; Hardware design languages; Image edge detection; Parity check codes; Syntactics; TV;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location :
Xiamen
ISSN :
2162-7541
Print_ISBN :
978-1-61284-192-2
Electronic_ISBN :
2162-7541
Type :
conf
DOI :
10.1109/ASICON.2011.6157199
Filename :
6157199
Link To Document :
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