Title :
FPGA interconnect timing library based on the statistical method
Author :
Meng, Xiangzhi ; Chen, Liguang ; Zhou, Hao ; Wang, Jian ; Yang, Meng ; Lai, Jinmei
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Abstract :
This paper presents a statistical method to build up interconnect timing library of static timing analysis for FPGA design. To overcome a large number of negative values in the traditional interconnect timing library, the statistical method is introduced. The experimental results show that the proposed method could improve the positive ratio and achieve up to 22.35% on average. Compared to the tested delay results on the FPGA chip, the delay error rate can be reduced from 13.58% to 11%.
Keywords :
error statistics; field programmable gate arrays; integrated circuit design; integrated circuit interconnections; logic design; FPGA chip; FPGA design; FPGA interconnect timing library; delay error rate; static timing analysis; statistical method; Field programmable gate arrays; Histograms; FPGA; Static Timing Analysis; statistical method; timing library;
Conference_Titel :
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location :
Xiamen
Print_ISBN :
978-1-61284-192-2
Electronic_ISBN :
2162-7541
DOI :
10.1109/ASICON.2011.6157204
