Nanoscale electrical and physical study of polycrystalline high-κ dielectrics and proposed reliability enhancement techniques

Grain boundaries (GBs) in polycrystalline high-κ (HK) dielectric materials affect the electrical performance and reliability of advanced HK-based metal-oxide-semiconductor (MOS) devices. In this work, we present a localized study comparing the electrical conduction through grains and GBs for CeO₂ and HfO₂-based HK dielectrics using scanning tunneling microscopy (STM) and transmission electron microscopy (TEM) at the nanometer scale, in conjunction with macroscopic MOS capacitor device level analysis. Nanoscale STM conduction analysis clearly reveals faster degradation at GB sites and their vulnerability to early percolation. Multi-layer HK dielectric stacks (capping of La₂O₃ on CeO₂ and dual-layer ZrO₂/HfO₂) are proposed as an effective technique to significantly enhance the time-dependent dielectric breakdown (TDDB) robustness of advanced HK metal gate (MG) stacks.