On-chip clock network using interconnected and coupled ring oscillators

All synchronous systems use a clock distribution network covering a large section of the integrated circuit and handling the fastest frequencies of the device. In this work, the performance of interconnected and coupled ring oscillator arrays working as clock distribution networks is analyzed. The use of interconnected three-delay stages rings are proposed even for chip lengths from 4 to 24 mm. Typical 3.3 V AMS 0.35 mum CMOS N-well process parameters were used for the design and fabrication. Experimental results of 16 non-expanded and expanded interconnected ring oscillators agree with simulation.