A control scheme for a 65nm 32×32b 4-read 2-write register file

This paper describes a control scheme for a 32×32bit 4-read, 2-write register file operating in 1.25GHz with TSMC 65nm LP (low-power) process. Signals from the timing control module can tolerate short clock pulse, which ensures that the register file can work well on high clock frequency. Due to the fact that the delay of the word-line driver in this design is easy to match, a dummy driver as well as a dummy cell is used to generate the enable signal of sense amplifier. And this self-timing approach has small area overhead introduced by the dummy circuits (only about 0.24% of the total cell area). Results show that this approach reduces the required timing margin and power consumption compared with the inverter-chain technique. As a result, about 8% of read speed improvement and 10.8% of power reduction could be achieved.