Implementation of enhanced CDMA utilizing low complexity joint detection with iterative processing

Computationally efficient joint detection in CDMA packetized communication is considered. The joint detection is based on iterative cancellation and utilizes only low complexity individual data receivers. The savings in complexity compared to other alternatives proposed in the literature is due to an encoding scheme known as partition spreading that can be decoded using algorithms that are similar to well-known turbo and sum-product decoding. Besides having a low computational complexity, the technique offers near-far resistant performance and can achieve higher system loads than conventional CDMA. The low complexity of these component receivers allows a large number of users to be implemented onto a single FPGA. A Virtex-IV on a Lyrtech Development board is used to implement a test bed for this PS-CDMA system. The implementation focuses on area optimization to give 50 users in a single Virtex-IV with 84% slice utilization and a maximum aggregate throughput of 192Mb/s. The measured performance of this prototype is compared against theoretical results on PS-CDMA in environments with varying power levels. An FPGA resource-performance analysis is given.