DocumentCode
3383256
Title
Design of a reconfigurable network interface processor
Author
Zhang, Lei ; Li, Tao ; Li, Zhentao ; Jiang, Lin
Author_Institution
Coll. of Electron. Eng., Xi´´An Univ. of Posts & Telecom, Xi´´An, China
fYear
2011
fDate
25-28 Oct. 2011
Firstpage
755
Lastpage
759
Abstract
A reconfigurable architecture for networking equipment interface is proposed. This processor is field programmable and its implementation is based on a model of arithmetic augmented finite state machine (AFSM). A structured realization of the AFSM is presented in the paper. This processor is specially designed for interfaces on low layers, such as the physical convergence layer.
Keywords
finite state machines; microprocessor chips; reconfigurable architectures; arithmetic augmented finite state machine; field programmable; networking equipment interface; physical convergence layer; reconfigurable architecture; reconfigurable network interface processor; structured realization; Optics; Dynamically reconfigurable processor; automata; network interface;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location
Xiamen
ISSN
2162-7541
Print_ISBN
978-1-61284-192-2
Electronic_ISBN
2162-7541
Type
conf
DOI
10.1109/ASICON.2011.6157315
Filename
6157315
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