Title :
An architectural survey and modeling of data cache memories in Verilog HDL
Author_Institution :
Fac. of Electron. & Telecommun., Politehnica Univ. of Bucharest, Romania
Abstract :
In this paper two data cache architectures-a direct-mapped write-through data cache and a direct-mapped, write-through, write buffering data cache-are presented followed by a synthesized implementation of these data cache models. Strategies for testing, results of simulations with Verilog-XLTM and methods of architectural improvement are also given
Keywords :
cache storage; hardware description languages; memory architecture; Verilog HDL; data cache memory architecture; direct-mapped write-through data cache; direct-mapped write-through write buffering data cache; simulation model; Hardware design languages; Hazards; Laboratories; Pipelines; Random access memory; Read-write memory; Reduced instruction set computing; Signal processing; System buses; Testing;
Conference_Titel :
Semiconductor Conference, 1999. CAS '99 Proceedings. 1999 International
Conference_Location :
Sinaia
Print_ISBN :
0-7803-5139-8
DOI :
10.1109/SMICND.1999.810448
