High throughput area-efficient SoC-based forward/inverse integer transforms for H.264/AVC

In this paper, high throughput area-efficient system-on-chip-based (SoC) forward/inverse integer transform (FIT/IIT) modules for H.264/AVC are proposed. High throughput can be achieved by pipelining quantization/rescaling and FIT/IIT blocks; while efficient area is possible by reusing architecture of all four transforms and using buffers for smoothening multiplications and reducing the number of multipliers and quantization/rescaling hardware. With the support of an Application Specific Instruction Processor (ASIP) and 2 built-in-RAM DMACs, the proposed FIT/IIT modules can perform both 4×4 and 8×8 transforms, and 2×2 and 4×4 Hadamard transforms of DC coefficients. Compared to the reported designs in 0.18 μm technology, the proposed FIT and IIT modules score higher Data Throughput per Unit Area (DTUA), and operate on each 8×8 block including I/O in 8 cycles, at 162.1 and 230.9 MHz, respectively.