Design and analysis of a multiprocessor system with extended fault tolerance

Author

Min, Byoung-Joon ; Shin, Sang-Seok ; Rim, Kee-Wook

Author_Institution

Dept. of Comput. Sci., Inchon Univ., South Korea

fYear

1995

fDate

28-30 Aug 1995

Firstpage

301

Lastpage

307

Abstract

Hardware approaches to fault-tolerance in designing a scalable multiprocessor system are discussed. Each node is designed to support multi-level fault-tolerance enabling a user to choose the level of fault-tolerance with a possible resource or performance penalty. Various tree-type interconnection networks using switches are compared in terms of reliability, latency, and implementation complexity. A practical duplicate interconnection network with the increased reliability is proposed in consideration of implementation issues under the physical constraint

Keywords

computational complexity; fault tolerant computing; multiprocessing systems; multiprocessor interconnection networks; extended fault tolerance; implementation complexity; latency; multiprocessor system; performance penalty; reliability; scalable multiprocessor system; tree-type interconnection networks; Application software; Fault detection; Fault tolerance; Fault tolerant systems; Hardware; Microprocessors; Multiprocessing systems; Multiprocessor interconnection networks; Parallel processing; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Distributed Computing Systems, 1995., Proceedings of the Fifth IEEE Computer Society Workshop on Future Trends of

Conference_Location

Cheju Island

Print_ISBN

0-8186-7125-4

Type

conf

DOI

10.1109/FTDCS.1995.524998

Filename

524998