Comparison of performance parameters of SRAM designs in 16nm CMOS and CNTFET technologies

CMOS devices are scaling down to nano ranges resulting in increased process variations and short channel effects which not only affect the reliability of the device but also performance expectations. Carbon Nanotube Field Effect Transistor (CNTFET) is a very promising and superior technology for its applications to circuit design. In this paper we intend to evaluate and compare the performance parameters of a traditional 6T SRAM cell between a predictive 16nm Complementary Metal Oxide Semiconductor (CMOS) technology and CNTFET. The model used to simulate CNT transistor is a tentative model from the researchers of Stanford University, which is not yet practically implemented. Since the dimensions of MOSFETS are reduced aggressively, it is essential to know the potential of what both the technologies have to offer, with their least dimensions available. The SRAM design uses the smallest transistors possible and is also susceptible to reliability issues and process variations, making it an ideal benchmark circuit to compare the two technologies. Our simulations results show that CNTFET based SRAM design is a viable design to choose compared to its CMOS counterpart. The results show that there is a 52.7% increase in SNM of the memory cell. Meanwhile, the cell becomes 5% faster. These results clearly justify that CNTFET is more suitable for circuit design rather than MOSFETs, although both the models under consideration are predictive models. This comparative study would definitely help us choose better technology alternatives in near future.