Impact of MOS threshold-voltage mismatch in current-steering DACs for CT ΣΔ modulators

This paper studies the impact of MOS threshold-voltage (V_th) mismatch in the switch pairs of the current-steering DAC used in the feedback path of continuous-time (CT) ΣΔ modulators. The V_th mismatch causes an asymmetric feedback pulse, whose effect is investigated both for return-to-zero (RZ) and non-return-to-zero (NRZ) feedback DACs, with and without dynamic element matching (data-weighted averaging, DWA). All cases except RZ DAC with DWA show a large degradation in both SNDR and SFDR performance, while a RZ DAC with DWA displays an (almost) ideal performance. A mismatch-aware DAC model has been developed in VerilogA, showing an excellent agreement with component-level spectre simulations and enabling a fast exploration of the design space.