A 2GHz 65nm CMOS digitally-tuned BAW oscillator

Author

Guillot, P. ; Philippe, P. ; Berland, C. ; Bercher, J.-F.

Author_Institution

Innovation Centre in RF, NXP Semicond., Caen

fYear

2008

fDate

Aug. 31 2008-Sept. 3 2008

Firstpage

722

Lastpage

725

Abstract

The design of a 2GHz reference frequency oscillator in a 65nm CMOS process using a Bulk Acoustic Wave resonator is presented. The oscillator implements digital frequency control using a switched capacitor bank in parallel to the resonator. The tuning range is up to 4MHz with a minimum step of 1.6kHz. The oscillator core is designed to reach low phase noise (-128dBc/Hz at 100kHz offset) at low power consumption (0.9mW) using a differential topology. It is followed by a low noise divider for output at 500MHz with a phase noise of -140dBc/Hz at 100kHz offset.

Keywords

CMOS digital integrated circuits; acoustic resonators; bulk acoustic wave devices; oscillators; CMOS digitally-tuned BAW oscillator; CMOS process; bulk acoustic wave resonator; digital frequency control; frequency 2 GHz; reference frequency oscillator; size 65 nm; switched capacitor bank; Acoustic waves; Capacitors; Electrodes; Oscillators; Phase noise; Q factor; Radio frequency; Semiconductor device noise; Solids; Tuning;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on

Conference_Location

St. Julien´s

Print_ISBN

978-1-4244-2181-7

Electronic_ISBN

978-1-4244-2182-4

Type

conf

DOI

10.1109/ICECS.2008.4674955

Filename

4674955