A 40 Mbps H.264/AVC CAVLC decoder using a 64-bit multiple-issue video parsing coprocessor

Author

Choi, Soonwoo ; Park, Jason J K ; Koo, Moonmo ; Kim, Daewoong ; Chae, Soo-Ik

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea

fYear

2010

fDate

27-29 Sept. 2010

Firstpage

105

Lastpage

108

Abstract

In this paper, we describe a programmable CAVLC decoder implemented with a video parsing coprocessor. The video parsing coprocessor is a VLIW processor that issues multiple instructions and supports condition-controlled instructions to efficiently program control intensive algorithms and customized instructions for bit operations and table matching. The complexity of the parsing coprocessor is 92 Kgates logic circuits with 7 KB SRAM and its operating frequency is 200 MHz when synthesized with a 130 nm CMOS technology. The CAVLC decoder, when operated at 192 MHz, can decode a bitstream at the rate of 40 Mbps, which corresponds to the level 4.1 of H.264/AVC full HD 1080p.

Keywords

coprocessors; instruction sets; program compilers; video coding; 64-bit multiple-issue video parsing coprocessor; H.264/AVC CAVLC decoder; VLIW processor; bit operations; condition-controlled instructions; control intensive algorithms; frequency 192 MHz; frequency 200 MHz; multiple instructions; size 130 nm; table matching; Algorithm design and analysis; Birds; CMOS technology; Decoding; Earth; Hardware; Manuals;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference (SOCC), 2010 IEEE International

Conference_Location

Las Vegas, NV

ISSN

Pending

Print_ISBN

978-1-4244-6682-5

Type

conf

DOI

10.1109/SOCC.2010.5784729

Filename

5784729