A 1.2 V 70 mA low drop-out voltage regulator in 0.13 µm CMOS process

A low drop-out (LDO) voltage regulator with a built-in bandgap is proposed in this paper and fabricated in 0.13-μm CMOS technology. The load regulation and drop-out voltage are reduced by enlarging the pass transistor. The headroom of the chip area is reduced by eliminating the miller capacitor of the two-stage Operational Transconductance Amplifier (OTA) for the error amplifier, the loop of the LDO is compensated by a large off-chip capacitor. The input voltage range is from 1.313 V to 1.5 V with a drop-out voltage of 113 mV for a 70 mA of load current. A load regulation of 7 mV and undershoot of 3 mV for a load current step from 1 mA to 70 mA with a 1-μs rise-up time is measured. The measured quiescent current is about 93 μA for a load current of 70 mA. The effective die area is 0.35 mm² including the testing pads.