Implementation of a hardware-efficient EEG processor for brain monitoring systems

This paper presents a complexity-efficient architecture for an EEG signal separation processor incorporating ICA with lossless data compression. An average correlation result of 0.9044 is achieved while transmitted EEG data bandwidth and power consumption are reduced by 41.6%. The chip area, operating frequency, and estimated power consumption of the proposed EEG architecture in UMC 90nm SP-HVT CMOS technology are 1,133 by 1,133 um², up to 32MHz, and approximately 0.70mW at 0.9V supply voltage and 5 MHz operating frequency, respectively.