Mixed-voltage I/O buffer using 0.35 μm CMOS technology

A 0.9 V to 5.0 V (0.9/1.2/1.8/2.5/3.3/5 V) mixed-voltage-tolerant I/O buffer carried out using CMOS 2P4M 0.35 mum process is proposed in this paper. By using a Dynamic gate bias generator to provide appropriate gate voltages for the output stage composed of stacked PMOS and stacked NMOS, the I/O buffer can transmit the signal with higher voltage level (VDDH). Besides, a new floating N-well circuit is proposed to remove the body effect at the output PMOS. Moreover, a Dynamic driving detector is used to balance the turn-on voltages for the PMOS and NMOS in the output stage. The duty cycle of the output signal of the proposed I/O buffer can then be equalized for VDDIO biased at low voltage. The maximum output speed of the proposed design is simulated to be 110/125/110/80/50/20 MHz for VDDIO = 5.0/3.3/2.5/1.8/1.2/0.9 V, respectively. The static power consumption is merely 553 nW in the worst simulation case of [SS, 100degC].