Title :
Efficient high-throughput architectures for high-speed parallel scramblers
Author :
Chen, JianWei ; Lin, Hongchin ; Tang, Yun-Ching
Author_Institution :
Dept. of Electr. Eng., Nat. Chung Hsing Univ., Taichung, Taiwan
fDate :
May 30 2010-June 2 2010
Abstract :
A generalized algorithm with efficient architectures for high-speed parallel scramblers with reduced registers is proposed. The algorithm can be applied to any scrambler polynomials with three terms to achieve small numbers of registers and fan-outs. The critical paths only have one register and one XOR gate, which are merged into a dynamic differential circuit for implementation. The results show that more than 50% chip area can be reduced in comparison with literatures, and the power dissipation is only 3.7mW at 1.6GHz with 16 parallel outputs, which is equivalent to 25.6Gbps, using TSMC 0.18 μm CMOS technology.
Keywords :
CMOS logic circuits; logic gates; polynomials; CMOS technology; TSMC; XOR gate; critical paths; dynamic differential circuit; frequency 1.6 GHz; high-speed parallel scramblers; high-throughput architectures; power 3.7 mW; reduced registers; scrambler polynomials; size 0.18 mum; CMOS technology; Circuits; Energy consumption; Optical fiber communication; Personal communication networks; Polynomials; Power dissipation; Registers; Synchronous generators; Wide area networks;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537678
