Title :
Hardware implementation of the double-tree scan architecture
Author :
Schemm, Nathan ; Balkir, Sina ; Seth, Sharad
Author_Institution :
Dept. of Electr. Eng., Univ. of Nebraska-Lincoln, Lincoln, NE, USA
fDate :
May 30 2010-June 2 2010
Abstract :
In a scan-based test architecture, the scan power and and test data volume can be reduced by utilizing a double tree scan (DTS) architecture. This paper presents a novel hardware implementation of the DTS architecture and compares the hardware overhead with the conventional scan architecture. The implementation proposed utilizes a clock structure which greatly decreases the number of clocked flip-flops and thereby reduces power consumption. A test chip is designed and fabricated in a 0.5 μm CMOS technology to verify the power saving properties of the architecture.
Keywords :
CMOS integrated circuits; clocks; flip-flops; integrated circuit design; integrated circuit testing; logic design; CMOS technology; DTS architecture; clock structure; clocked flip-flops; double-tree scan architecture; hardware implementation; hardware overhead; power consumption; power saving property; scan power; scan-based test architecture; size 0.5 mum; test chip; test data volume; CMOS technology; Circuit testing; Clocks; Compaction; Computer architecture; Energy consumption; Flip-flops; Hardware; Logic testing; Power dissipation;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537687
