DocumentCode :
3385155
Title :
A power management methodology for high-level synthesis
Author :
Lakshminarayana, Ganesh ; Raghunathan, Anand ; Jha, Niraj K. ; Dey, Sujit
Author_Institution :
Dept. of Electr. Eng., Princeton Univ., NJ, USA
fYear :
1998
fDate :
4-7 Jan 1998
Firstpage :
24
Lastpage :
29
Abstract :
In this paper, we present a power management technique targeted towards high-level synthesis of data-dominated behavioral descriptions. Our method is founded on the observation that variable assignment can significantly affect power management opportunities in the synthesized architecture. Based on this observation, we present a procedure for constraining variable assignment, so that the functional units in the synthesized architecture do not execute any spurious operations. Unlike many previously proposed power management techniques, our method does not have an attendant performance penalty. Experimental results indicate savings of up to 52.5% in power consumption over already power-optimized architectures, at area overheads not exceeding 6.4%
Keywords :
high level synthesis; architecture; behavioral description; high-level synthesis; power management; variable assignment; Clocks; Energy consumption; Energy management; High level synthesis; Laboratories; Logic circuits; National electric code; Power dissipation; Power system management; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on
Conference_Location :
Chennai
ISSN :
1063-9667
Print_ISBN :
0-8186-8224-8
Type :
conf
DOI :
10.1109/ICVD.1998.646573
Filename :
646573
Link To Document :
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