On the output events in concurrent error detection schemes

Extra circuitry for concurrent error detection (CED) schemes is becoming an essential feature as IC technologies continue to scale. Soft errors have emerged as an important challenge in the nanoscale design and several works are dedicated to quantify the CED effective enhancement in systems dependability, but none of them makes a comprehensive description of the output events that can occur in such schemes. In this paper we propose a methodology to evaluate circuits with CED, including the time penalty as a relevant metric even in hardware redundancy techniques. We have also proposed a FPGA-based emulation platform to improve run-time performance.