An LDMOS class E power amplifier designed by Source/Load-Pull technique

Author

He, Jin ; Ren, Dehao

Author_Institution

Chengdu Univ. of Inf. Technol., Chengdu, China

fYear

2009

fDate

23-25 July 2009

Firstpage

742

Lastpage

745

Abstract

The source/load-pull design process of the input/output impedance matching network of a class E power amplifier is introduced in this paper. A design example of an LDMOS device MRF21010 at VHF band is given, and the results of the amplifier performance are simulated as a function of gate bias voltage, DC supply voltage, input power and frequency. The gain of 13.78 dB, the peak drain efficiency of 84.41%, and the power added efficiency of 80.08% are obtained whereupon the output power level is 38.78 dBm at 500 MHz.

Keywords

MOS integrated circuits; VHF amplifiers; impedance matching; integrated circuit design; power amplifiers; DC supply voltage; LDMOS device MRF21010; VHF band; class E power amplifier; frequency 500 MHz; gain 13.78 dB; gate bias voltage; input-output impedance matching network; load-pull design process; source design process; Circuit simulation; Energy consumption; Helium; Impedance matching; Information technology; Power amplifiers; Power generation; Process design; Spaceborne radar; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Circuits and Systems, 2009. ICCCAS 2009. International Conference on

Conference_Location

Milpitas, CA

Print_ISBN

978-1-4244-4886-9

Electronic_ISBN

978-1-4244-4888-3

Type

conf

DOI

10.1109/ICCCAS.2009.5250395

Filename

5250395