Title :
Proceedings. 23rd IEEE VLSI Test Symposium
Abstract :
The following topics are discussed: VLSI testing; memory BIST; delay testing; multisite testing; memory testing; high-speed testing and clock skew compensation; design-for-testability for SoC; wireless applications; test data compression and self-testing; analog testing; soft errors; defect-oriented testing; adaptive test; high speed I/O testing; reliable and fault-tolerant wireless sensor networks; FPGA and MEMS testing; IP in wireless testing; RF testing; nanometer technologies; low-power testing; nanometer and circuit-level effects; test resource partitioning; reliability; test scheduling; I/sub DDQ/ testing; and power supply noise analysis.
Keywords :
VLSI; automatic testing; built-in self test; data compression; design for testability; fault diagnosis; field programmable gate arrays; integrated circuit reliability; integrated circuit testing; integrated memory circuits; micromechanical devices; nanotechnology; system-on-chip; FPGA testing; I/sub DDQ/ testing; IP; MEMS testing; RF testing; SoC; VLSI testing; adaptive testing; analog testing; circuit-level effects; clock skew compensation; defect-oriented testing; delay testing; design-for-testability; fault-tolerant wireless sensor networks; high speed I/O testing; high-speed testing; low-power testing; memory BIST; memory testing; multisite testing; nanometer effects; nanometer technologies; power supply noise analysis; reliability; self-testing; soft errors; system on chip; test data compression; test resource partitioning; test scheduling; wireless applications; wireless testing;
Conference_Titel :
VLSI Test Symposium, 2005. Proceedings. 23rd IEEE
Conference_Location :
Palm Springs, California, USA
Print_ISBN :
0-7695-2314-5
