DocumentCode
3386471
Title
Parametric reliability test: wafer surface contamination study
Author
Bersuker, Gennadi ; Guan, Jay ; Gale, Glenn ; Lysaght, Patrick ; Riley, Deborah ; Huff, Howard R.
Author_Institution
Int. SEMATECH, Austin, TX, USA
fYear
2002
fDate
21-24 Oct. 2002
Firstpage
29
Lastpage
31
Abstract
Reliability tests are usually labor and time intensive that makes it difficult to provide reliability assessments in a cost effective and timely manner. On the other hand, the test should be sufficiently sensitive to satisfy experimental requirements. In order to address these concerns, we developed a completely automated parametric end-of-line reliability test, which is intended to be applicable with gate oxides in the range of 2.0- 5.0 nm. In this study on the effect of carbon contamination on device electrical properties, the results of the automated gate oxide reliability test were correlated to the transistor performance and physical analysis data.
Keywords
MOSFET; semiconductor device reliability; semiconductor device testing; surface contamination; 2.0 to 5.0 nm; C; MOS transistor; automated parametric end-of-line reliability test; carbon contamination; electrical properties; gate oxide; wafer surface contamination; Automatic testing; Costs; Current measurement; Dielectric substrates; Electric breakdown; Performance evaluation; Pollution measurement; Stress measurement; Surface contamination; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Reliability Workshop Final Report, 2002. IEEE International
Print_ISBN
0-7803-7558-0
Type
conf
DOI
10.1109/IRWS.2002.1194227
Filename
1194227
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