A vector quantizer with fully pipelined data and control flow

Previously proposed linear array structures for vector quantization tend to treat memory access as an independent issue, implying that load and store operations are performed through separate data and control pins. For most applications, it is essential to adaptively update code vectors during normal operation. We present a design where global wiring is restricted to power and clock supplies, thus making the architecture truly scalable. Since data and control signals are not broadcast but propagated through local connections, they have to be accessed by the host via processing elements at the array boundary. The contribution of this paper is to ensure these desirable properties while maintaining its pipelined and parallel operation. An important objective is to demonstrate that our proposed linear array architecture using a data-driven control scheme exhibits flexibility and expandability which make it very attractive for VLSI implementation.